library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;

entity dummy is
  port (clk : in std_logic;
		c_w : out std_logic_vector(7 downto 0);
		addr_w : out std_logic_vector(11 downto 0);
		wr_en : out std_logic);
end entity;

architecture rtl of dummy is
	signal ctr : integer;
begin
	process(clk)
	begin
		if (rising_edge(clk)) then
			ctr <= ctr + 1;
		end if;
	end process;

	c_w <= std_logic_vector(to_unsigned(ctr,8));
	addr_w <= std_logic_vector(to_unsigned(ctr, 12));
	wr_en <= '1';
end rtl;

